Aprisa P&R
Aprisa P&R is a platform for automatic placement and routing of digital ICs, covering both the top hierarchical level of the project and the physical implementation of individual blocks of complex digital ICs. The core of Aprisa technology is an optimized detailed trace architecture and unified hierarchical database specifically designed for projects with 28nm and below technology nodes. Using the latest advances in physical IC design technology, Aprisa provides fast and high-quality performance, power consumption, chip area, and reliability for complex digital IC projects.
Detailed architecture with a focus on tracing
As designs move into the 16nm and lower region, the resistance of conductors and transition holes becomes a factor that has a critical impact on IC performance. Signal delays in the interconnects and other factors need to be carefully considered at the tracing stage. Because of this, it is necessary to have a mechanism for accounting for these parameters throughout the tracing process.
The Aprisa architecture includes a single operational data model that is used throughout the placement and tracing process, providing operational data exchange between stages such as placement optimization, timing tree optimization, detailed final tracing, etc. Precise matching of the data model to a particular stage and point in time of the tracing process improves the quality of results, reduces the number of iterations and speeds up the tracing process by 2 or more times as compared to similar systems from other vendors.
Leading Factory Certification
The Aprisa platform is fully certified by leading factories, including TSMC, for advanced technology standards down to 7nm. During the certification process, Aprisa tested and certified new technologies that are unparalleled in the world. These technologies, deliver high performance, power consumption and chip area criteria while reducing the design cycle and getting to market quickly.
