The Tanner custom analog-to-digital IC design route is one of the most widely used in the world, both in terms of the number of users and the availability of libraries at leading factories. It is fully integrated with such leading Mentor Graphics solutions in its fields as AFS, OASYS RTL, Nitro-SoC, Calibre and others. Tanner Routing is easy to lea and easily adapts to individual user requirements.

The flow includes a circuit editor with an extended set of functions, a topology editor, integration with the leading analog-to-digital simulation system (AFS, Symphony), the Calibre platform - the gold standard in design rule control, physical verification and parasitic parameter extraction.

The design process begins with the creation of a schematic, its verification, followed by analog or analog-to-digital simulation and the development of a crystal topology, its physical verification, and production preparation. Libraries for the most popular sub-nanometer technology processes are certified by leading factories for use in the Tanner flow.

Tanner is integrated with virtually all analog and analog-to-digital simulators, including simulators from other vendors, allowing engineers to choose the solution that suits them best.

Tanner includes, in addition to traditional analog-to-digital IC design, complete solutions for designing MEMS and photonics ICs that are used in many mode applications, such as the IoT.

Key features and benefits

• Comprehensive design flow from the creation of the schematic to the tapeout
• Support for major standards: OpenAccess, iPDK, TCL, Python
• PDKs for the most popular design standards certified by major foundries
• Full integration with the Calibre platform for physical verification and production preparation
• Large selection of simulators: T-Spice, Eldo, AFS, Symphony, Questa, third party simulators

Analog IC design

The Tanner solution is a reliable and repeatedly tested (tens of thousands of designed and manufactured ICs over 30 years of existence), which provides a complete solution at relatively low acquisition and technical support costs. Tanner includes all phases of development - circuit design, transistor-level modeling, topology design and physical verification, and production preparation. More than 25 leading factories offer PDKs certified for the Tanner route.

S-Edit

The S-Edit schematic editor includes an advanced toolbox for developing analog circuits, including the most complex mode designs. After circuit creation and preliminary verification, the user can move on to the simulation phase with a rich selection of simulators: T-Spice, Eldo, AFS and others.

The simulation process is managed by the Tanner Designer tool. It provides a convenient visualization of simulation results, with which engineers can quickly analyze which blocks passed the initial specification test and which did not. This approach effectively manages the convergence process of functional verification. Simulation results can also be output as reports in eXcel or LibreOffice formats.

Main features and advantages of the schematic editor

• Comprehensive design route from the creation of the schematic to the issuance of the tapeout
• Support for major standards: OpenAccess, iPDK
• Support for importing and exporting schematics in all major industry standards
• Linux and Windows support
• Simulation management, including multiprocess mode
• Convenient output of simulation results
• Large selection of simulation systems: T-Spice, Eldo, AFS, Questa and others
• Support for multiple applications for project version control

Download a description of the S-Edit tool

L-Edit

The L-Edit layout editor supports hierarchical designs and offers an advanced set of tools for creating project topology, including advanced features such as rearranging components, highlighting individual areas, creating script-based macros, and more. L-Edit supports automatic schematic topology generation (SDL), which completely eliminates LVS errors associated with manual wiring of cells. In addition, SDL provides fast schematic correction in case of changes (ECO). As a final step, Calibre is used for final physical verification before the design is transferred to fabrication.

Key features and benefits

• Comprehensive solution for IS topology development, including hierarchical projects
• Support for major standards: OpenAccess, iPDK
• Support for multiple applications for project version control
• Extended set of Boolean operations with polygons
• Full integration with Calibre for final physical verification
• Support for C++, TCL and Python scripts

Download L-Edit tool description

Design of mixed ICs

Tanner includes all stages of analog-to-digital IC development - circuit design, modeling at the transistor and RTL level, topology development and physical verification, production preparation. One of the main tasks in this case is to simplify as much as possible the development of the digital part of the project.

The schematic of the analog part of the project is created with the S-Edit editor, which includes an advanced toolbox for developing analog circuits, including the most complex mode designs. Digital blocks described in Verilog or VHDL are "plugged" into the schematic as macros. After the complete description of the project has been completed, it can be simulated at the transistor level with one of the simulators - T-Spice, Eldo, AFS. These simulators are integrated with the Questa digital simulation platform, allowing for joint analog-to-digital simulation.

For projects with a large digital part, the Digital Implementer option is used, which includes the OASYS RTL digital block synthesis module and the Nitro P&R placement and routing module.

Digital Implementer is fully integrated with the L-Edit layout editor, making it an ideal tool for mixed analog-digital design projects such as IoT. It has a simple user interface, is easy to learn, and includes an option to automatically configure the design process, which is an important benefit for analog circuit designers who are not too familiar with the digital design process.

Then the planning, placement and tracing of the digital part of the project can be done in two ways. The first is when the engineer sets the chip parameters, clearances, trace channel widths, power bus routing requirements directly in Digital Implementer. In the second case these parameters are set in the topological editor L-Edit or via a location description file in DEF format. Direct tracing is performed in the Digital Implementer using the above settings.

The technological parameters of the library cells can be imported in the standard formats LEF, Liberty, PTF, and the Verilog netlist is supplemented by the requirements to the timing parameters by connecting a corresponding constraint file.

Key features and benefits

• The Place and Route module supports operation under time constraints and includes advanced algorithms for the synchronization tree layout
• Support for low power IC design methodology
• The planner takes into account the geometry of the power circuits
• Linux and Windows support
• Ability to synthesize scan chains for DFT applications
• Ability to adapt to user requirements by writing scripts in TCL
• Ability to import process and time parameters in standard formats

Download Tanner Digital Implementer package description

MEMS IC design

Tanner offers a gold-standard design and simulation solution for 3D MEMS devices. The design process begins with the creation of the MEMS device topology in the L-Edit editor. One of the advantages of the Tanner route is that a single design environment is used to develop the device topology, its 3D modeling and production preparation, which also provides the creation of MEMS component libraries for their subsequent reuse. At the same time, the MEMS design process is fully integrated into the IC design route, making it possible to quickly and efficiently develop a complete device design in a single package.

The L-Edit layout editor includes all the functionality needed to develop MEMS devices. The ability to create curvilinear topological elements, an advanced mechanism of Boolean operations with topological elements and the use of parameterized cells make the process of creating MEMS devices simple and efficient.

The Tanner solution allows you to design MEMS devices based on their exhaustive simulation, eliminating the costly physical prototyping step. At the same time, an extended set of simulators provides the ability to simulate MEMS and ICs together in a single simulation session.

The parameterized approach also includes the ability to simulate in preparation for production, which, as repeatedly tested by leading factories, ensures the correct product in the first manufacturing cycle.

Download a description of the MEMS design flow

Photonic IC design

The Tanner flow provides an integrated solution for both conventional and photonics-based IC design. This solution covers all stages of design - circuit development, modeling, design, and topology verification.

The script-driven LightSuite Photonic Compiler performs automatic hybrid tracing of electrical and optical lines, reducing the time to produce the final topology from weeks to hours. The L-Edit Photonics option integrated with the compiler traces blocks that do not contain optical lines in a traditional format.

Simulation of photonics circuits as well as mixed optoelectronic circuits can be performed using simulators supplied by our partners. The corresponding design kits are certified by leading factories.

Layout design automation

The LightSuite Photonic Compiler is the only tool to date that provides automatic tracing of ICs with embedded photonics. It includes several tracing programs that automatically trace both optical and electrical lines. High tracing speed allows tracing about 500 optical components per hour. The user can choose a tracing program as well as different tracing algorithms from the built-in compiler, for example, tracing with fixed interconnection length. Connecting Calibre RealTime directly during placement and tracing ensures DRC-correct results.

The LightSuite Photonic Compiler supports several modes of operation:

• With the help of control scripts, specialists fully control the process of IC placement and tracing with embedded photonics
• Automatic circuit-based topology generation to create blocks that do not contain photonics
• Designing in experimental mode allows to create a test project with the subsequent possible change of parameters of separate cells and their testing
• Designing optical lines in an intermediate substrate that can house both optical and conventional components

The main features and benefits of the LightSuite Photonic Compiler

• High tracing speed allows you to create alternative versions based on the "what if" principle
• The factories have certified a large number of design kits (PDKs)
• Support for standards, including OpenAccess
• Support for the popular Python language for scripting
• Ensuring DRC-correct topology with Calibre RealTime
• Linux OS Support

Designing custom photonics ICs

The L-Edit Photonics option complements the powerful L-Edit topology editor with special features for manually designing embedded optical components. This option allows you to quickly create optical elements and interconnections, using the traditional drag-and-drop technology used in traditional topology editors. Engineers can select optical components from PDKs supplied by factories, place them on the chip and connect them with optical waveguides. The creation of overlaps is allowed. The L-Edit Photonics option automatically precisely connects the waveguides to the element pins, ensuring a reliable connection. Using that editor, electrical components can be placed and connected. After the topology of the project is fully completed, the netlist is extracted for further simulation.

The L-Edit Photonics option supports several modes of operation

• Manual topology creation without using a schematic
• Manual topology creation based on the schematic
• Automatic topology generation based on the schematic

Key features and benefits of L-Edit Photonics

• Supports manual creation of the layout without a schematic. Topology in this case is the "golden" component of the project database
• Support for traditional circuit-based topology creation with the S-Edit editor
• Generating a netlist for simulation
• For simulation we use products from our partners: Luceda, Lumerical, Optiwave, VPIphotonics
• Numerous design kits (PDKs) certified by leading factories
• Linux and Windows OS support

Topology verification

Verification is performed with Calibre, which uses equation-based rules to verify optical elements, allowing verification of curved waveguide structures.

Photonics simulation

Simulation is performed using applications supplied by our partners: Luceda, Lumerical, Ansys, Optiwave, VPIphotonics. These applications also support mixed optical-transistor modeling.