General Information

The Aprisa-RTL digital IC logical and physical synthesis suite supports designs of virtually unlimited capacity, while providing high quality results by optimizing the design at the top level of abstraction and using a built-in planning and placement engine. It achieves high quality results in a short amount of time through rapid iterations of planning and placement followed by synthesis that consider the physical parameters of the object being synthesized.

Most of the known RTL synthesis packages use optimization routines at the netlist level. Aprisa-RTL uses optimization at the top abstraction level, which provides a much better synthesis result. The patented PlaceFirst technology provides prepositioning (prior to synthesis) that allows the synthesis to take into account temporal and spatial constraints. In addition, RTL optimization is much faster, enabling designs of 100 million gates or more to be synthesized in orders of magnitude less time than synthesizers delivered by major competitors.

Project size and synthesis time

Aprisa-RTL introduces a new approach to Digital Design Synthesis-all data from RTL to the level of placed gates and macros are analyzed and optimized in a single run of the synthesis procedure. The entire synthesis of a design with a capacity of tens of millions of gates, from raw netlist to placed gates, takes just a few hours.

The large capacity of the projects is offset by the high synthesis speed. The key to the high capacity and high synthesis speed is RTL-level optimization technology that also improves the quality of the results and reduces the number of synthesis iterations. The optimization of projects greater than 100 million pins itself is done in a single run. For projects of equal capacity, Aprisa-RTL finite synthesis time is an order of magnitude shorter than traditional synthesis packages from other vendors.

RTL-level chip planning

The new technology used by Aprisa-RTL is to pre-plan the chip layout already at RTL level and take into account parameters like data bus structure, latency, power and chip footprint limitations, trace channel limits, etc. The built-in planning editor automatically places macros, pins and pads while analyzing the constraints on individual chip areas, trace no-go areas, blocked traces and other physical constraints. At the same time, bandwidth constraints for trace channels, excessive delays, static and dynamic power consumption, DFT requirements and space constraints are analyzed so that if any parameter is violated, the required change can be made at an early stage of synthesis. Pre-planning from Aprisa-RTL can be used directly in the physical synthesis step, dramatically reducing the time to final placement for silicon-on-chip implementation.

Lower power consumption

Aprisa-RTL includes a full range of power-consumption-oriented functionality, including support for logic libraries with multiple trigger thresholds, clock gating, UPF-based multiple power level projects, and more. The synthesis process installs all necessary switching level shift circuits, isolation cells, and hold registers, depending on the requirements specified in the UPF project description. During the synthesis process, Aprisa-RTL analyzes the static and dynamic power consumption and, if necessary, makes appropriate changes to optimize it. To minimize the dynamic power consumption, a special logic is generated for clock gating based on the analysis of the VCD file and the variable clock frequency data. Areas of excessive power consumption are highlighted in the layout plan and a cross-reference report between the topology and RTL code can be generated that allows for quick troubleshooting.

High quality synthesis

Aprisa-RTL uses unique pre-positioning technology to optimize RTL. Unlike traditional synthesis tools that first do the synthesis and then optimize the result at the valve level, Aprisa-RTL simultaneously optimizes the RTL code partitioning based on preplacement, resulting in a more optimal result immediately. It combines high quality results based on pre-placement physics and the ability to iterate quickly to make changes and validate them.

Aprisa-RTL first synthesizes RTL code into virtual physical blocks. Each of these blocks is optimized separately at the level of placed valves. If necessary, the initial partitioning can be changed until all the requirements of the top-level RTL specification are met. The output of Aprisa-RTL is a valve netlist and DEF file as input for the placement and tracing step.

Upper abstraction-level optimization technology and built-in planning and placement engine deliver unparalleled results in terms of supported design capacity, synthesis time, quality of results and consideration of physical parameters throughout all synthesis steps.