ModelSim simulates behavioral, RTL and gate-level code, providing improved design quality and debugging performance through platform-independent compilation. The single-core simulator technology allows you to transparently mix VHDL and Verilog in the same project. It provides an unprecedented level of verification capabilities in an efficient HDL simulator and is ideal for verifying small to medium-sized FPGA projects - especially those with complex, mission-critical functionality.
ModelSim's advanced code coverage capabilities provide valuable metrics for systematic verification. In addition, ModelSim's ease of use lowers barriers to the use of verification resources. All coverage information is stored in a highly efficient UCDB database. Coverage results can be viewed interactively, after simulation, or after combining multiple simulation runs.

Comprehensive support for Verilog, SystemVerilog for Design, VHDL, and SystemC provides a solid foundation for a verification environment for designs in one or more languages. The easy-to-use and unified environment provides FPGA developers with the advanced capabilities needed for debugging and simulation.
ModelSim makes it easy to find design flaws with its intelligently designed debugging environment that efficiently displays design data for analysis and debugging in all hardware description languages. Its extensive set of intuitive features for Verilog, VHDL and SystemC make it the ideal choice for ASIC and FPGA design.