Nowadays, functional verification is becoming the most complex and costly stage of system-on-chip (SoC) design. The time-to-market of a product is becoming a determining factor. And the increasing complexity of designs is placing ever greater demands on functional verification, affecting related areas such as reducing power consumption while increasing performance, intellectual property protection, verifying correct operation of the object in safety-critical projects, etc. All this being said, functional verification takes up 75-80% of the design cycle and is becoming a dominant factor in getting a product to market on time.

Mentor A Siemens Business IP Block Verification library (Questa VIP) is making a significant contribution to the functional verification problem by providing verified models of the standard protocols that developers can use to verify their own blocks working in conjunction with standard IP. Because these models have already been repeatedly tested and certified, the developer can be confident that the DUT (Design-under-Test)-IP interface works correctly. Questa VIP provides:

-        Compatible with UVM methodology

-        Support for all major simulators

-         Ready-to-use test sequences for interface testing in an open format

-Supports a methodology for planning tests and ensuring completeness of coverage

Support for the UVM standard enables multiple use of Standard Interface IP block models for functional verification including all the necessary modeling, debugging and completeness of coverage tools to significantly speed up the verification process.

Questa VIP improves quality and reduces verification time through the use of a certified model library of standard interfaces. This frees engineers from the drudgery of creating, debugging and verifying those models, such as BFMs (Bus Functional Models) and other verification components, by allowing them to focus on the unique part of the project.