The Visualizer™ Debug Environment is a high-performance, scalable, context-sensitive environment for testbench and object debugging that supports all kinds of functional verification, including modeling, hardware emulation and prototyping as well as assertion and power analysis.

The app is easy to use and automates the debugging process in the SoC and FPGA verification process.

Visualizer is fully integrated with both the Questa simulator and the Veloce hardware emulation system, supports Verilog, SystemVerilog and VHDL, and provides all the capabilities you need to analyze waveforms, source code and cross-references. In addition to being intuitive and easy to use, Visualizer arms the engineer with powerful tools to increase productivity in debugging objects at the SystemVerilog/UVM, transaction, RTL, valve level, including low power project verification.

Scalability

• Fast simulation with full observability of signals
• Data preparation for modeling, emulation and validation in silicon

RTL debugging

• Intelligent error source analysis using TimeCone technology and reverse event tracing
• Advanced event search and highlighting system across the entire design under test and testbench

UVM methodology support

• Support for debugging SystemVerilog classes both interactively and in post-debug mode
• Support for all SystemVerilog classes, debugging UVM testbench, asserts, synchronous transactions

Debugging low-power systems

• Intuitive visualization of UPF parameters in the context of the project
• Output of the complete table of overlapping zones with different power ratings