Products → Functional Verification
Questa transforms the functional verification process, dramatically increasing its productivity and resource management efficiency. Based on several advanced technologies and integration with the Veloce hardware emulation system, Questa is the ideal tool for verifying complex systems-on-chip (SoC).
Questa provides intelligent test generation that delivers higher quality simulation results with fewer tests. This significantly improves verification productivity. The Verification Management option reduces regression testing and complete coverage time from hours to minutes. Questa makes testbench development easier with automatic generation of coverage models.
Questa offers a comprehensive verification solution for projects that include specific power consumption optimization schemes. The Questa Power Aware Simulation (PASim) option verifies the architecture of power optimization schemes in static and dynamic mode. Quest CDC verifies systems with multiple synchronization domains and controlled power. Questa Formal provides exhaustive logic analysis in power management circuits. The Questa Verification Management option controls that low-power projects are verified within a given timeframe in the overall functional coverage plan.
For today's complex projects, debugging is one of the most critical and critical verification steps. Questa, in combination with the Questa Visualizer Debug option for debugging the testbench and the object under test, and in combination with the Codelink option for software and hardware debugging, provides maximum productivity, comprehensive coverage, and automation of the entire SoC debug cycle.
Questa Formal options offer the unique ability to detect hidden, complex errors and increase the completeness of functional coverage through exhaustive formal analysis. Questa includes a range of formal verification options-from fully automated applications, such as verification of projects with multiple sync domains, code coverage completeness analysis and automatic formal property verification, to verification of user-written assertions. Formal methods combined with traditional modeling can improve the productivity of the verification process and provide confidence that the SoC being developed is fully verified.
Questa is the first functional verification platform that fully supports UVM methodology and enables automated development of universal SystemVerilog class-based testbench and easy-to-use interface with the under test object, combined with cross-references between the testbench, the RTL code under test and the waveform.
Questa allows you to view the hierarchy of project components, class definition trees and other UVM options specific to your testbench, making it easier to understand the entire verification environment. In conjunction with the UVM Framework, UVM Connect and Questa VIP options, Questa provides engineers with everything they need to efficiently and quickly perform functional verification on the design under test.
SGS-TUV Saar, a company that specializes in qualifying design and verification tools for safety-critical projects, has certified the Questa platform, including the Questa Verification Management and Questa CDC options, as providing a high level of functional safety and assurance for all projects requiring ISO 26262 certification. The Questa simulation process provides comprehensive verification for security-critical projects. The Questa Verification Management option allows you to monitor the completeness of functional coverage by collecting and analyzing relevant metrics. The Questa CDC option detects and corrects any meta-stability effects in projects with multiple synchronization domains.